As is well known, solid state storage devices such as SD card or solid state drive (SSD) are widely used in a variety of electronic devices. Generally, a solid state storage device comprises a controlling circuit and a non-volatile memory.
Moreover, a NAND-based flash memory is one kind of non-volatile memory. Depending on the amount of data to be stored, the NAND-based flash memories may be classified into three types, i.e. a single-level cell (SLC) flash memory, a multi-level cell (MLC) flash memory and a triple-level cell (TLC) flash memory. The SLC flash memory can store only one bit of data per cell. The MLC flash memory can store two bits of data per cell. The TLC flash memory can store three bits of data per cell.
FIG. 1 is a schematic functional block diagram illustrating a conventional solid state storage device. As shown in FIG. 1, the solid state storage device 10 is connected with a host 14 through an external bus 12. Generally, the external bus 12 is a USB bus, a SATA bus, a PCIe bus, or the like. Moreover, the solid state storage device 10 comprises a controlling circuit 101 and a non-volatile memory 105. The controlling circuit 101 is connected with the non-volatile memory 105 through an internal bus 107. According to a command from the host 14, the controlling circuit 101 stores the received write data into the non-volatile memory 105, or the controlling circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 14.
The controlling circuit 101 further comprises an error correction code (ECC) unit 104 for correcting the error bits of the read data. After the error bits of the read data are corrected, accurate read data are transmitted to the host 14.
FIG. 2A schematically illustrates the architecture of cells in the non-volatile memory of the solid state storage device. The non-volatile memory 105 has a memory array composed of plural cells. Each cell includes a floating gate transistor. The memory array comprises plural word lines WL(n−1), WL(n) and WL(n+1) for controlling respective rows of cells. When one of the plural word lines is activated, a selected row corresponding to the activated word line is determined. According to the on/off states of the floating gate transistors of the cells in the selected row, the storing states of the cells are determined. Moreover, the cells are SLC, MLC or TLC.
Generally, the floating gate transistor of each cell has a floating gate to store hot carriers. A threshold voltage (VTH) of the floating gate transistor is determined according to the amount of the stored hot carriers. If a floating gate transistor has a higher threshold voltage, it means that a higher gate voltage is required to turn on the floating gate transistor. Whereas, if a floating gate transistor has a lower threshold voltage, it means that the floating gate transistor can be turned on by a lower gate voltage.
During a program cycle of the solid state storage device, the amount of hot carriers to be injected into the floating gate is controlled by the controlling circuit 101, so that the floating gate transistor is correspondingly changed. During a read cycle, the controlling circuit 101 determines the storing state of the floating gate transistor by judging whether the floating gate transistor is turned on.
FIG. 2B schematically illustrates the threshold voltage distribution curves of the SLC flash memory in different storing states. Generally, each cell of the SLC flash memory has two storing states E and A according to the amount of the injected hot carriers. Before the hot carriers are injected into the cell, the cell has the storing state E (e.g., a logic state “1”). After the hot carriers are injected into the cell, the cell has the storing state A (e.g., a logic state “0”). The threshold voltage of the cell in the storing state A is higher, and the threshold voltage of the cell in the storing state E is lower. After an erase cycle, the cell is returned to the storing state E where no hot carriers are injected into the cell.
Moreover, each cell of the MLC flash memory has four storing states, and each cell of the TLC flash memory has eight storing states. Hereinafter, only the cells of the SLC flash memory will be described. It is noted that the concepts of the present invention are also applied to the MLC flash memory and the TLC flash memory.
In practical, even if many cells are in the same storing state during the program cycle, the threshold voltages of these cells are not all identical. That is, the threshold voltages of these cells are distributed in a specified distribution curve with a median threshold voltage. As shown in FIG. 2B, the cells in the storing state E have a median threshold voltage VTHE (e.g. 0V), and the cells in the storing state A have a median threshold voltage VTHA (e.g. 20V). In other words, a greater number of the cells in the storing state A have the median threshold voltage VTHA (e.g. characteristics of the SLC flash memory, a first sensing voltage Vs1 is defined. During the read cycle, the controlling circuit 101 applies the first sensing voltage Vs1 to the word line, and the storing state of each cell of the SLC flash memory is realized by judging whether the cell is turned on. If the threshold voltage of the cell is lower than the first sensing voltage Vs1 and the cell is turned on, the controlling circuit 101 judges that the cell is in the storing state E. Whereas, if the threshold voltage of the cell is higher than the first sensing voltage Vs1 and the cell fails to be turned on, the controlling circuit 101 judges that the cell is in the storing state A.
For example, in the non-volatile memory 105 of FIG. 2B, p cells are programmed to have the storing state E, and w cells are programmed to have the storing state A.
When the p cells in the storing state E are detected according to the first sensing voltage Vs1, only (p−q) cells with the threshold voltages lower than the first sensing voltage Vs1 are confirmed to have the storing state E. However, the other q cells with the threshold voltages higher than the first sensing voltage Vs1 are erroneously judged to have the storing state A. Similarly, when the w cells in the storing state A are detected according to the first sensing voltage Vs1, only (w−x) cells with the threshold voltages higher than the first sensing voltage Vs1 are confirmed to have the storing state A. However, the other x cells with the threshold voltages lower than the first sensing voltage Vs1 are erroneously judged to have the storing state E.
As mentioned above, during the read cycle of the solid state storage device 10, the controlling circuit 101 applies the first sensing voltage Vs1 to the non-volatile memory 105. In the generated read data, the storing states of (q+x) cells are erroneously judged and these (q+x) cells are also referred as error bits. If the number of the erroneously-judged cells is small, the ECC unit 104 can correct the erroneously-judged cells and output the accurate read data. However, if the number of the erroneously-judged cells is large, the ECC unit 104 cannot effectively correct the erroneously-judged cells. Under this circumstance, the controlling circuit 101 cannot output the accurate read data.
Generally, the conventional ECC unit 104 comprises a BCH decoder. The controlling circuit 101 with the BCH decoder uses a single first sensing voltage Vs1 to judge the storing state of the non-volatile memory 105.
Moreover, the BCH decoder is a hard decoder for performing a hard decoding process. After the first sensing voltage Vs1 is provided to the non-volatile memory 105, the output data is referred as hard data. The BCH decoder corrects the error bits of the hard data according to the hard data and generates the accurate read data.
FIG. 2C is a flowchart illustrating a hard decoding process of the conventional solid state storage device. In case that the ECC unit 104 of the controlling circuit 101 contains the BCH decoder, the solid state storage device 10 may perform the hard decoding process. Firstly, the controlling circuit 101 provides a default first sensing voltage Vs1 to the non-volatile memory 105 and performs a decoding operation according to the generated hard data (Step S302).
If the decoding operation is successfully completed by the ECC unit 104 according to the hard data (Step S304), it means that the error bits in the hard data can be corrected. Consequently, the controlling circuit 101 outputs the read data (Step S310). Whereas, if the decoding operation is not successfully completed according to the hard data (Step S304), the error bits in the hard data cannot be effectively corrected because the number of error bits is too large. Consequently, the controlling circuit 101 performs a read retry step (Step S305).
While the read retry step S305 is performed, the controlling circuit 101 updates the first sensing voltage Vs1, provides the updated first sensing voltage Vs1 to the non-volatile memory 105, and performs a decoding operation according to the generated hard data (Step S306). Then, a step S308 is performed to judge whether the decoding operation is successfully completed.
In particular, during the process of performing the read retry step S305, the controlling circuit 101 sequentially provides M values (e.g., 20 values) of the first sensing voltage Vs1 to the non-volatile memory 105. The M values of the first sensing voltage Vs1 are previously stored in the controlling circuit 101 before the solid state storage device 10 leaves the factory. That is, these M values are sequentially used as the updated values of the first sensing voltage Vs1. If the decoding operation is successfully completed according to the hard data corresponding to the updated first sensing voltage Vs1, the controlling circuit 101 outputs the read data (Step S310). Whereas, if the decoding operation is not successfully completed according to the hard data corresponding to all of the M updated values of the updated first sensing voltage Vs1, the controlling circuit 101 generates a failed message to indicate that the read retry step fails. In other words, the steps S306 and S308 are performed M times at most. Moreover, if the controlling circuit 101 confirms that the read retry step fails, the hard decoding process fails.
Moreover, all of the M updated values of the first sensing voltage Vs1 are stored in a retry table of the conventional solid state storage device 10. While the controlling circuit 101 performs the read retry step, it is necessary to acquire the updated first sensing voltage Vs1.
After the solid state storage device 10 leaves the factory, if the solid state storage device has been written and erased many times, the threshold voltage distribution curves of the storing state of all cells in the non-volatile memory 105 are possibly changed. Under this circumstance, the median threshold voltage is shifted. Since it is difficult to realize the change of the threshold voltage distribution curve, the hard decoding process of employing the updated values of the first sensing voltage Vs1 in the retry table is very time-consuming. Under this circumstance, the throughput of the solid state storage device 10 is largely reduced.